According to Moore's law, the number of Transistor count that a chip can hold doubles every two years. However, Moore's law is not just a technical problem of doubling the number of Transistor count on the same chip. Moore's law implies that power consumption and performance will be greatly improved as chip integration density doubles. In the past 50 years, the semiconductor industry has been developing in accordance with Moore's law, because the three elements of chips - price, power consumption and performance - are always linked.

In the foreseeable future, although the semiconductor industry can continue to prove the correctness of Moore's law, when it develops below the most advanced 28nm technology node, it will encounter headwind to block the pace of progress, because after 28nm, the technical complexity and manufacturing cost will be greatly improved. Taking into account the three factors of price, power consumption, and performance, fully depleted silicon on insulation layer (FD-SOI) is the best choice for the development of chip manufacturing processes towards 10 nanometer technology nodes.

For chip manufacturers, end product manufacturers and consumer electronics manufacturers, FD-SOI meets the requirements of the three elements of Moore's law, and is a market tested solution, because the 28nm FD-SOI manufacturing process has been put into mass production. At present, STMicroelectronics is deploying 14 nm FD-SOI technology, which is expected to be put into mass production after 2015, while 10 nm FD-SOI technology is still in the research and development stage.

Ultimately, cost is the decisive factor in whether any manufacturing process can bring investment returns. Compared to the traditional bulk CMOS manufacturing process, FD-SOI is a new technology that uses slightly more expensive chips. However, its simpler structure makes it the most cost-effective manufacturing process among technology nodes below 30 nanometers. If a chip is made using 28 nanometer technology, under the same options and metal layer conditions, FD-SOI requires 38 masks, while some substrate CMOS require up to 50 masks. FD-SOI reduces manufacturing processes by 15% and delivery times by 10%, which can significantly reduce costs. In addition, reducing the number of masks and manufacturing processes helps to improve product yield, thereby further reducing costs.

Compared to FinFET technology, FD-SOI has more obvious advantages. FD-SOI is backward compatible with traditional mature substrate CMOS processes. Therefore, engineers can continue to use existing development tools and design methods when developing the next generation of products, and it is very easy to transform the existing 300mm wafer manufacturing plant into an FD-SOI wafer production line, as most equipment can be reused.

Obviously, FD-SOI encounters the least technical and cost resistance in the manufacturing process that complies with Moore's law above 10 nm nodes. Consumer electronics manufacturers and other original equipment manufacturers have been affected by Moore's law for decades. They expect semiconductor manufacturers to improve chip performance at the same price. If the price decreases, it will be better. Unless the situation is extremely special, equipment manufacturers cannot accept high prices. The key issue is whether FD-SOI can fulfill its promise. In addition to price advantages, FD-SOI using state-of-the-art technology can also improve performance and power consumption to meet the needs of end users in different application fields, such as consumer electronics, infrastructure, and even unimaginable future applications.

In addition to being "simpler", the powerful performance of transistors is an inherent advantage of FD-SOI, and the breakdown forward body bias (FBB) and wider voltage regulation range are its unique characteristics. Simply put, when the chip performance is fixed, FBB and a wider voltage regulation range can reduce power consumption, or when the power consumption is fixed, FBB can improve the chip performance. In fact, FBB forms another transistor within one transistor, which can only be achieved by FD-SOI, while FinFET cannot.

FBB features will bring great benefits to Consumer electronics using FD-SOI system chips. In the application design of trying to make full use of frequency fixed components, high-performance components and different operating modes, the dynamic tuning function of FD-SOI chips can make the performance and power consumption reach the best state.

In the field of infrastructure, the electricity consumption of a data center is greater than that of a medium-sized city. Analysts estimate that the total power consumption of all data centers worldwide is equivalent to the power generation of 30 nuclear power plants [1], and FBB allows application systems to dynamically adjust power consumption/leakage current/operating frequency based on the load of the data centers. In this way, the energy consumption of the data center will be proportional to the workload, and ultimately, FD-SOI can reduce the power consumption of the data center by up to 50%.

Although power consumption is important (especially in infrastructure areas such as data centers that consume a lot of electricity), it can only rank second in importance rankings after performance. FD-SOI can also meet the high-performance requirements of the market. After switching from a 28 nanometer substrate CMOS to a 28 nanometer FD-SOI, the circuit speed has increased by up to 35%. Even with significant performance improvements, the heat dissipation rate of FD-SOI transistors remains low due to lower leakage current, wider voltage regulation range, and improved chip energy efficiency through FBB. This results in smaller heat dissipation and longer battery life for terminal devices, significantly reducing the indirect operating costs of high power consuming infrastructure such as data centers, such as computer cooling expenses.

Energy efficiency is equally important for the emerging Internet of Things. To monitor and track every object, the Internet of Things requires the deployment of billions of intelligent sensors worldwide and ensuring that these sensors are always connected to the Internet. Considering the scale and potential of the Internet of Things, up to billions of sensors must operate efficiently, ensuring high energy efficiency even when working at low pressures. As the most energy-efficient feasible solution, FD-SOI can meet the energy-saving requirements of the Internet of Things.

Because the ASICs and system chips using FD-SOI have inherent advantages in price, power consumption and performance, STMicroelectronics has obtained 15 related design projects. As the ecosystem composed of OEM and IP partners continues to expand in 2014, STMicroelectronics will win more design projects.

A Complete Proof of Moore's law

The semiconductor industry today can foresee 10 nanometer nodes to prove the method of Moore's law. To comply with Moore's law, we need a complete method that can take advantage of the price, power consumption and performance of the basic manufacturing process. Therefore, FD-SOI naturally becomes a substitute for substrate CMOS and will continue to create self value, while also creating value for the massive global industrial ecosystem that relies on chips.